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NVIDIA DRIVE OS Linux SDK API Reference
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6.0.10.0 Release
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Go to the documentation of this file.
13 #ifndef NVSIPL_CAP_STRUCTS_H
14 #define NVSIPL_CAP_STRUCTS_H
60 #if (NV_IS_SAFETY == 0)
159 #define NVSIPL_CAP_MIN_IMAGE_WIDTH 640U
162 #define NVSIPL_CAP_MAX_IMAGE_WIDTH 3848U
165 #define NVSIPL_CAP_MIN_IMAGE_HEIGHT 480U
168 #define NVSIPL_CAP_MAX_IMAGE_HEIGHT 2168U
171 #define NVSIPL_CAP_MIN_FRAME_RATE 10U
174 #define NVSIPL_CAP_MAX_FRAME_RATE 60U
179 #define NVSIPL_PIXEL_ORDER_LUMA (0x00000001U)
181 #define NVSIPL_PIXEL_ORDER_YUV (0x00000002U)
183 #define NVSIPL_PIXEL_ORDER_YVU (0x00000003U)
185 #define NVSIPL_PIXEL_ORDER_YUYV (0x00000004U)
187 #define NVSIPL_PIXEL_ORDER_YVYU (0x00000005U)
189 #define NVSIPL_PIXEL_ORDER_VYUY (0x00000006U)
191 #define NVSIPL_PIXEL_ORDER_UYVY (0x00000007U)
193 #define NVSIPL_PIXEL_ORDER_XUYV (0x00000008U)
195 #define NVSIPL_PIXEL_ORDER_XYUV (0x00000009U)
197 #define NVSIPL_PIXEL_ORDER_VUYX (0x0000000AU)
201 #define NVSIPL_PIXEL_ORDER_ALPHA (0x00000011U)
203 #define NVSIPL_PIXEL_ORDER_RGBA (0x00000012U)
205 #define NVSIPL_PIXEL_ORDER_ARGB (0x00000013U)
207 #define NVSIPL_PIXEL_ORDER_BGRA (0x00000014U)
209 #define NVSIPL_PIXEL_ORDER_RG (0x00000015U)
213 #define NVSIPL_PIXEL_ORDER_RGGB (0x00000021U)
215 #define NVSIPL_PIXEL_ORDER_BGGR (0x00000022U)
217 #define NVSIPL_PIXEL_ORDER_GRBG (0x00000023U)
219 #define NVSIPL_PIXEL_ORDER_GBRG (0x00000024U)
222 #define NVSIPL_PIXEL_ORDER_RCCB (0x00000025U)
224 #define NVSIPL_PIXEL_ORDER_BCCR (0x00000026U)
226 #define NVSIPL_PIXEL_ORDER_CRBC (0x00000027U)
228 #define NVSIPL_PIXEL_ORDER_CBRC (0x00000028U)
231 #define NVSIPL_PIXEL_ORDER_RCCC (0x00000029U)
233 #define NVSIPL_PIXEL_ORDER_CCCR (0x0000002AU)
235 #define NVSIPL_PIXEL_ORDER_CRCC (0x0000002BU)
237 #define NVSIPL_PIXEL_ORDER_CCRC (0x0000002CU)
240 #define NVSIPL_PIXEL_ORDER_CCCC (0x0000002DU)
244 #define NVSIPL_PIXEL_ORDER_BGGI_RGGI (0x0000002EU)
246 #define NVSIPL_PIXEL_ORDER_GBIG_GRIG (0x0000002FU)
248 #define NVSIPL_PIXEL_ORDER_GIBG_GIRG (0x00000030U)
250 #define NVSIPL_PIXEL_ORDER_IGGB_IGGR (0x00000031U)
252 #define NVSIPL_PIXEL_ORDER_RGGI_BGGI (0x00000032U)
254 #define NVSIPL_PIXEL_ORDER_GRIG_GBIG (0x00000033U)
256 #define NVSIPL_PIXEL_ORDER_GIRG_GIBG (0x00000034U)
258 #define NVSIPL_PIXEL_ORDER_IGGR_IGGB (0x00000035U)
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_A
Specifies CSI port A.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW8
Specifies RAW 8.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_GH
Specifies CSI port GH.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_E
Specifies CSI port E.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RGB888
Specifies RGB.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_F
Specifies CSI port F.
@ NVSIPL_BITS_PER_PIXEL_14
Specifies 14 bits per pixel.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_G
Specifies CSI port G.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_A1
Specifies CSI port A with 1 lane.
NvSiplBitsPerPixel
Specifies bits per pixel.
NvSiplBitsPerPixel bitsPerPixel
Holds number of bits per pixel for NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_x input format types.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_8
Specifies User defined 8 (0x37).
NvSiplCapInputFormatType inputFormatType
Holds capture input format type.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_D1
Specifies CSI port D with 1 lane.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_YUV422_10
Specifies YUV 4:2:2 10 bits.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_7
Specifies User defined 7 (0x36).
@ NVSIPL_BITS_PER_PIXEL_10
Specifies 10 bits per pixel.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW7
Specifies RAW 7.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_6
Specifies User defined 6 (0x35).
NvSiplCapInterfaceType
Specifies the capture interface type for the CSI interface.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_D
Specifies CSI port D.
NvSiplCapCsiPhyMode
Specifies the CSI PHY mode.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_2
Specifies User defined 2 (0x31).
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_H
Specifies CSI port H.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_YUV444
Specifies YUV 4:4:4.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW16
Specifies RAW 16.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_C
Specifies CSI port C.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_5
Specifies User defined 5 (0x34).
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_G1
Specifies CSI port G with 1 lane.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_4
Specifies User defined 4 (0x33).
@ NVSIPL_BITS_PER_PIXEL_16
Specifies 16 bits per pixel.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_YUV422
Specifies YUV 4:2:2 8 bits.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_H1
Specifies CSI port H with 1 lane.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_C1
Specifies CSI port C with 1 lane.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW10
Specifies RAW 10.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_MAX
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_B1
Specifies CSI port B with 1 lane.
NvSiplCapInputFormatType
Specifies the capture input format type.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_EF
Specifies CSI port EF.
@ NVSIPL_BITS_PER_PIXEL_20
Specifies 20 bits per pixel.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW14
Specifies RAW 14.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_E1
Specifies CSI port E with 1 lane.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW6
Specifies RAW 6.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW20
Specifies RAW 20.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_3
Specifies User defined 3 (0x32).
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_1
Specifies User defined 1 (0x30).
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW12
Specifies RAW 12.
@ NVSIPL_CAP_CSI_CPHY_MODE
Specifies that CSI is in CPHY mode.
@ NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW12RJ
Specifies RAW 12 Right Justified.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_B
Specifies CSI port B.
@ NVSIPL_BITS_PER_PIXEL_8
Specifies 8 bits per pixel.
@ NVSIPL_BITS_PER_PIXEL_12
Specifies 12 bits per pixel.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_CD
Specifies CSI port CD.
@ NVSIPL_CAP_CSI_DPHY_MODE
Specifies that CSI is in DPHY mode.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_F1
Specifies CSI port F with 1 lane.
@ NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_AB
Specifies CSI port AB.
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