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  • NVIDIA DRIVE OS Linux SDK API Reference

    6.0.10.0 Release
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    osi_est_config Struct Reference

    Detailed Description

    OSI Core EST structure.

    Definition at line 185 of file nvethernetrm_export.h.

    Data Fields

    nveu32_t en_dis
     Valid values ate 0 and 1 o to disable EST and 1 to enable EST. More...
     
    nveu32_t btr [2]
     64 bit base time register if both values are 0, take ptp time to avoid BTRE index 0 for nsec, index 1 for sec Valid values are from 0 to UNIT32_MAX for each index More...
     
    nveu32_t btr_offset [2]
     64 bit base time offset index 0 for nsec, index 1 for sec 32 bits for Seconds, 32 bits for nanoseconds (max 10^9) More...
     
    nveu32_t ctr [2]
     40 bits cycle time register, index 0 for nsec, index 1 for sec 8 bits for Seconds, 32 bits for nanoseconds (max 10^9) More...
     
    nveu32_t ter
     Configured Time Interval width(24 bits) + 7 bits extension register Valid values are from 1 to 0x7FFFFFFFU. More...
     
    nveu32_t llr
     size of the gate control list Max 256 entries valid value range (1-255) More...
     
    nveu32_t gcl [OSI_GCL_SIZE_256]
     data array 8 bit gate op + 24 execution time MGBE HW support GCL depth 256 More...
     

    Field Documentation

    ◆ btr

    nveu32_t osi_est_config::btr[2]

    64 bit base time register if both values are 0, take ptp time to avoid BTRE index 0 for nsec, index 1 for sec Valid values are from 0 to UNIT32_MAX for each index

    Definition at line 194 of file nvethernetrm_export.h.

    ◆ btr_offset

    nveu32_t osi_est_config::btr_offset[2]

    64 bit base time offset index 0 for nsec, index 1 for sec 32 bits for Seconds, 32 bits for nanoseconds (max 10^9)

    Definition at line 197 of file nvethernetrm_export.h.

    ◆ ctr

    nveu32_t osi_est_config::ctr[2]

    40 bits cycle time register, index 0 for nsec, index 1 for sec 8 bits for Seconds, 32 bits for nanoseconds (max 10^9)

    Definition at line 200 of file nvethernetrm_export.h.

    ◆ en_dis

    nveu32_t osi_est_config::en_dis

    Valid values ate 0 and 1 o to disable EST and 1 to enable EST.

    Definition at line 188 of file nvethernetrm_export.h.

    ◆ gcl

    nveu32_t osi_est_config::gcl[OSI_GCL_SIZE_256]

    data array 8 bit gate op + 24 execution time MGBE HW support GCL depth 256

    Definition at line 210 of file nvethernetrm_export.h.

    ◆ llr

    nveu32_t osi_est_config::llr

    size of the gate control list Max 256 entries valid value range (1-255)

    Definition at line 207 of file nvethernetrm_export.h.

    ◆ ter

    nveu32_t osi_est_config::ter

    Configured Time Interval width(24 bits) + 7 bits extension register Valid values are from 1 to 0x7FFFFFFFU.

    Definition at line 204 of file nvethernetrm_export.h.


    The documentation for this struct was generated from the following file:
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