CPU Paramaters

The CPU parameter settings contain the initial settings passed to CPU-Init FW. Contact NVIDIA before changing these settings.
Table 1. CPU Configuration
Fields Description
ccplex_platform_features CCPLEX platform features
cmu_misc_ctrl CCPLEX Miscellaneous unit Control data
cluster_misc_ctrl Cluster Misc Control
min_adc_fuse_rev minimum reliable ADC fuse revision
cpu_vmon CPU Voltage Monitor
pllx_data/pllx_refclk_khz PLLx Reference Clock freq in kHz
pllx_data/dsu_hpll_base DSU HPLL Base
pllx_data/dsu_hpll_misc_[0-7] DSU HPLL MISC [0-7]
pllx_data/cpu_hpll_base CPU HPLL Base
pllx_data/cpu_hpll_misc_[0-7] CPU HPLL MISC [0-7]
nafll_data/coeff_mdiv Input M divider; This should be set such that: CLOCKIN/MDIV <= 12800000 Hz
nafll_data/coeff_pdiv Glitchless linear pdivider
nafll_data/coeff_fll_frug_fast FLL frequency bandwidth control used in fast lock mode
nafll_data/coeff_fll_frug_main FLL frequency bandwidth control used in normal lock mode
nafll_data/cfg2_fll_init Initial CODE value for FLL = (FLL_INIT * 2)
nafll_data/cfg2_fll_ctrl_ldmem FLL_LOCK asserts after LDMEM clk_upd cycles of zero error, or error zero-crossings
nafll_data/cfg2_fll_switch_ldmem DVCO min detect timeout counter. If the DVCO runs at its lowest possible setting for LDMEM consecutive refclk/MDIV cycles, assert DVCO_MIN_REACHED and act as if it were locked
nafll_data/lut_sw_freq_req_sw_override_ndiv SW NDIV override controls
nafll_data/lut_sw_freq_req_ndiv SW Override for NAFLL NDIV
nafll_data/cfg1_vfgain Static NAFLL VFGAIN
avfs_refclk_khz AVFS reference clock speed, in kHz
dsu_lut_sw_freq_req SW override for dsu freq output to NAFLL
cpu_lut_sw_freq_req SW override for cpu freq output to NAFLL
scratch_freq_default Scratch frequency default
num_clusters_2core_pair_lockstep Cluster 2 Core Pair Lockstep
num_clusters_1core_pair_lockstep Cluster 1 Core Pair Lockstep
dsu_burst_policy DSU burst policy
cpu_burst_policy CPU burst policy