NvSIPLISPStructs.hpp

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/*
 * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */
 
#ifndef NVSIPLISPSTRUCTS_HPP
#define NVSIPLISPSTRUCTS_HPP
 
#include "NvSiplControlAutoDef.hpp"
 
namespace nvsipl
{
constexpr uint32_t NUM_GTM_SPLINE_POINTS = 18U;
 
struct NvSiplISPGlobalToneMapInfo
{
    bool enable;
    NvSiplISPSplineControlPoint gtmSplineControlPoint[NUM_GTM_SPLINE_POINTS];
};
 
constexpr uint32_t NVSIPL_LUMINANCE_CALIB_MATRIX_SIZE {4U};
 
constexpr uint32_t NVSIPL_CCM_MATRIX_SIZE {3U};
 
struct NvSiplControlInfo
{
    bool valid;
    float_t alpha;
    bool isLuminanceCalibrated;
    double_t luminanceCalibrationFactor;
    float_t luminanceCalibrationMatrix[NVSIPL_LUMINANCE_CALIB_MATRIX_SIZE][NVSIPL_LUMINANCE_CALIB_MATRIX_SIZE];
    SiplControlAutoAwbGain wbGainTotal;
    float_t cct;
    float_t brightnessKey;
    float_t sceneDynamicRange;
    float_t sceneBrightness;
    float_t rawImageMidTone;
    NvSiplISPGlobalToneMapInfo gtmSplineInfo;
    float_t ccm[NVSIPL_CCM_MATRIX_SIZE][NVSIPL_CCM_MATRIX_SIZE];
};
 
struct NvSIPLDownscaleCropCfg
{
    bool ispInputCropEnable {false};
    NvSiplRect ispInputCrop {};
 
    bool isp0OutputCropEnable {false};
    NvSiplRect isp0OutputCrop {};
 
    bool isp1OutputCropEnable {false};
    NvSiplRect isp1OutputCrop {};
 
    bool isp2OutputCropEnable {false};
    NvSiplRect isp2OutputCrop {};
 
    bool isp0DownscaleEnable {false};
    uint32_t isp0DownscaleWidth {0U};
    uint32_t isp0DownscaleHeight {0U};
 
    bool isp1DownscaleEnable {false};
    uint32_t isp1DownscaleWidth {0U};
    uint32_t isp1DownscaleHeight {0U};
 
    bool isp2DownscaleEnable {false};
    uint32_t isp2DownscaleWidth {0U};
    uint32_t isp2DownscaleHeight {0U};
 
};
 
} // namespace nvsipl
 
#endif // NVSIPLISPSTRUCTS_HPP