Display Serializer

The following sections describe the display serializer.

Configuring Video Timings

For both SST and MST mode, the mode timings that are used for each stream must be configured in Device Tree. Only one mode timing can be specified at a time for each video stream. The timings that are exposed in the EDIDs of the serializer and the panels connected to the downstream deserializer are completely ignored.

An example Device Tree fragment is shown below. In this example, a standard 1920x1080 at 60 Hz timing is specified for the first video stream, and a 1280x720 at 60 Hz timing is specified for the second video stream:


{
    display@13800000 {
        display-timings {
            display-connector-0 {
                dcb-index = <0>;

                stream-0 {
                    timings-phandle = <&mode_ss_1080p>;

                    superframe-info {
                        pipe_x_view: view-0 {
                            x = <0>;
                            y = <0>;
                            width = <1920>;
                            height = <1080>;
                            hfront-porch = <24>;
                            hback-porch = <40>;
                            hsync-len = <16>;
                            vfront-porch = <3>;
                            vback-porch = <18>;
                            vsync-len = <10>;
                        };

                        pipe_y_view: view-1 {
                            x = <1920>;
                            y = <0>;
                            width = <1920>;
                            height = <1080>;
                            hfront-porch = <24>;
                            hback-porch = <40>;
                            hsync-len = <16>;
                            vfront-porch = <3>;
                            vback-porch = <18>;
                            vsync-len = <10>;
                        };
                    };
                };

                stream-1 {
                    timings-phandle = <&mode_ss_1080p>;

                    superframe-info {
                        pipe_z_view: view-0 {
                            x = <0>;
                            y = <0>;
                            width = <1920>;
                            height = <1080>;
                            hfront-porch = <24>;
                            hback-porch = <40>;
                            hsync-len = <16>;
                            vfront-porch = <3>;
                            vback-porch = <18>;
                            vsync-len = <10>;
                        };

                        pipe_u_view: view-1 {
                            x = <1920>;
                            y = <0>;
                            width = <1920>;
                            height = <1080>;
                            hfront-porch = <24>;
                            hback-porch = <40>;
                            hsync-len = <16>;
                            vfront-porch = <3>;
                            vback-porch = <18>;
                            vsync-len = <10>;
                        };
                    };
                };
            };
        };

        mode_ss_1080p: 3840-1080-60Hz {
            clock-frequency-khz = <266640>;
            hactive = <3840>;
            vactive = <1080>;
            hfront-porch = <48>;
            hback-porch = <80>;
            hsync-len = <32>;
            vfront-porch = <3>;
            vback-porch = <18>;
            vsync-len = <10>;
            rrx1k = <60000>;
        };

        mode0: 1920-1080-60Hz {
            clock-frequency-khz = <148500>;
            hactive = <1920>;
            vactive = <1080>;
            hfront-porch = <88>;
            hback-porch = <148>;
            hsync-len = <44>;
            vfront-porch = <4>;
            vback-porch = <36>;
            vsync-len = <5>;
            rrx1k = <60000>;

        mode1: 1280-720-60Hz {
            clock-frequency-khz = <74250>;
            hactive = <1280>;
            vactive = <720>;
            hfront-porch = <110>;
            hback-porch = <220>;
            hsync-len = <40>;
            vfront-porch = <5>;
            vback-porch = <20>;
            vsync-len = <5>;
            rrx1k = <60000>;
        };
    };
};

In the preceding example:

display@13800000 is the overall parent node for the entire display device. This node already exists today.
- display-timings is used to specify which timings are used for each stream.
  - display-connector-0 specifies the timing information for the first display connector. If there are multiple display connectors present on the board that require fixed timings, then a new display-connector node must be created for each connector.
    - dcb-index specifies the logical index X of the DCB -> Display Devices -> Display Device X entry in the display DCB blob that this connector entry applies to. If there is only one display connector on the board, then dcb-index defaults to 0.
    - The stream nodes specify the phandle of the mode timing node that applies to the given video stream. It also optionally includes "superframe-info," which gives split-view details in that superframe.
- Each mode node contains the actual mode timing parameters used for a given video stream.
  - clock-frequency-khz: Pixel clock frequency in KHz
  - hactive: Horizontal active
  - vactive: Vertical active
  - hfront-porch: Horizontal front porch
  - hback-porch: Horizontal back porch
  - hsync-len: Horizontal sync width
  - vfront-porch: Vertical front porch
  - vback-porch: Vertical back porch
  - vsync-len: Vertical sync width
  - rrx1k": Refresh rate in units of 0.001 Hz
  - Each "stream" node can optionally contain superframe info that contains which details of split view
    - x: x offset of view in the superframe
    - y: y offset of view in the superframe
    - width: width of view
    - height: height of view
    - hfront-porch: Horizontal front porch
    - hback-porch: Horizontal back porch
    - hsync-len: Horizontal sync width
    - vfront-porch:Vertical front porch
    - vback-porch: Vertical back porch
    - vsync-len: Vertical sync width

Each display-connector can only have up to two stream nodes, and it is fine to specify two stream nodes even if the display serializer operates in SST mode because only the first stream node is consumed by the display driver. The extra node is ignored.

Configuring the Maxim DP Serializer Driver

If you are using the NVIDIA reference Maxim DP serializer driver, there are various ways to configure the driver by using Device Tree. As shown in the following example, a Device Tree fragment configures the Maxim DP serializer chip in MST mode:

i2c@31e0000 {
    status = "okay";
    maxim_ser: max_gmsl_dp_ser@40 {
        compatible = "maxim,max_gmsl_dp_ser";
        reg = <0x40>;
        status = "okay";
        max_gmsl_dp_ser-pwrdn = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
        ser-errb = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 7) 0>;
        dprx-link-rate = <0x1e>;
        dprx-lane-count = <0x4>;
        enable-mst;
        mst-payload-ids  = <0x1 0x3 0x2 0x4>;
        gmsl-stream-ids  = <0x0 0x1 0x2 0x3>;
        gmsl-link-select = <0x0 0x0 0x1 0x1>;        
        enable-gmsl3 = <0 1>;
        superframe-video-timings {		
                pipe-x {
			superframe-group = <0>;
			timings-phandle = <&pipe_x_view>;
			};
		pipe-y {
			superframe-group = <0>;
			timings-phandle = <&pipe_y_view>;
			};
		pipe-z {
			superframe-group = <1>;
			timings-phandle = <&pipe_z_view>;
			};
		pipe-u {
			superframe-group = <1>;
			timings-phandle = <&pipe_u_view>;
			};
	};
    };
        
};

A description of each of the preceding properties is as follows:

Required properties:
- compatible: Must be maxim,max_gmsl_dp_ser.
- reg: I2C address of the Maxim DP display serializer.
- gmsl-link-select: This property is an array of four unsigned 8-bit values that determines the GMSL output link to enable for each video pipe X, Y, Z, and U. The possible values for each pipe are:
  - 0x0 (Link A)
  - 0x1 (Link B)
  - 0x2 (Link A + B)
Optional properties:
- max_gmsl_dp_ser-pwrdn: GPIO pin number of the PWRDN pin. This pin is used to power up and power down the Maxim DP display serializer chip.
- dprx-link-rate: Configures the DP link rate of the serializer chip.
  The default value is 0x1E (HBR3). The possible values are:
  - 0xA (HBR)
  - 0x14 (HBR2)
  - 0x1E (HBR3)
- dprx-lane-count: Configures the DP lane count of the serializer chip.
  The default value is 0x4. The possible values are:
  - 0x1
  - 0x2
  - 0x4
- ser-errb: GPIO pin number of the ERRB pin. This pin is used for error and fault reporting by the serializer chip.
- enable-mst: This is a Boolean property. If this property is present, the driver will enable MST mode.
- mst-payload-ids: This property is an array of four unsigned 8-bit values, which represent MST payload IDs of pipe X, Y, Z, U. This property is mandatory if the enable-mst property is mentioned in device tree.
- gmsl-stream-ids: This property is an array of four unsigned 8-bit values, which represent GMSL stream IDs of pipe X, Y, Z, U. This property is mandatory if enable-mst property is mentioned in device tree.
- enable-gmsl3: This is a boolean property. When this property is set, GMSL3 capabilities are enabled.
- Superframe-video-timings: These are superframe video timings to be applied to each video pipe. So if this property is present then pipe-x and pipe-y properties must be present together OR pipe-z and pipe-uproperties must be present together. This is a restriction because with current support, a superframe can be either split to pipe-x and pipe-y OR to pipe-z and pipe-u. This is known as symmetric superframe splitting.
  - pipe-x: Superframe property for video pipe-x
    - superframe-group: This is an id of superframe from which a split view is applied to video pipe-x.
    - timings-phandle: This is video timings to be applied to video pipe-x so that the part of superframe can be routed to this video-pipe.
  - pipe-y: Superframe property for video pipe-y.
    - superframe-group: This is an id of superframe from which a split view is applied to video pipe-y.
    - timings-phandle: These are video timings to be applied to video pipe-y so that the part of superframe can be routed to this video-pipe.
  - pipe-z: Superframe property for video pipe-z.
    - superframe-group: This is an id of superframe from which a split view is applied to video pipe-z.
    - timings-phandle: These are video timings to be applied to video pipe-z so that the part of superframe can be routed to this video-pipe.
  - pipe-u: Superframe property for video pipe-u.
    - superframe-group: This is an id of superframe from which a split view is applied to video pipe-u.
    - timings-phandle: These are video timings to be applied to video pipe-u so that the part of superframe can be routed to this video-pipe.

Modeset Limitations

The Maxim DP display serializers do not support dynamic mode changes in MST mode without requiring a reset of the serializer chip in-between. In this context, a mode change refers to changing the number of video streams and/or the display timings that are used for each stream. As such, if the Maxim DP display serializers are configured in MST mode, it is recommended to always enable all video streams that will be used at once.

Configuring the Maxim HDMI Serializer

If you are using the NVIDIA Maxim HDMI serializer driver, there are various ways to configure the driver by using Device Tree, As shown in the following example:

i2c@31e0000 {
    status = "okay";
    maxim_ser: maxim_gmsl_hdmi_ser@40 {
        compatible = "maxim,maxim_gmsl_hdmi_ser";
        reg = <0x40>;
        status = "okay";
        maxim_gmsl_hdmi_ser-pwrdn = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
        ser-errb = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 7) 0>;
        enable_rclkout = <0x1>;
      };
};

A description of each of the preceding properties is as follows:

Required properties:
- compatible: Must be maxim,maxim_gmsl_hdmi_ser.
- reg: I2C register address of Maxim HDMI serializer.
- maxim_gmsl_hdmi_ser-pwrdn: GPIO pin number of the PWRDN pin. This pin is used to power up the Maxim HDMI display serializer chip.
- ser-errb: GPIO pin number of the ERRB pin. This pin is used for error and fault reporting by the serializer chip.
Optionals properties:
- enable_rclkout: RCLOUT signal is going as an input to camera deserializer and working as a clock source.

The Maxim HDMI display serializer does not support multiple links and by default uses the Link A of the serializer.

Configuring the TI Serializer Driver

If you use the NVIDIA reference TI serializer driver, there are several ways to configure the driver by using the device tree. The following example shows a device tree fragment that configures the TI serializer chip in SST mode:

      i2c@31e0000 { /* i2c8 */
		status = "okay";
		ti_ser: ti_fpdlink_dp_ser@18 {
			compatible = "ti,ti_fpdlink_dp_ser";
			reg = <0x18>;
			status = "okay";
			ti_fpdlink_dp_ser-pwrdn = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
			dprx-link-rate = <0x0A>;
			dprx-lane-count = <0x4>;
			timings-phandle = <&mode0>;
			fpd-link-select = <0x1 0x0>;
		};

The properties of the preceding example are described as follows:

Required properties:
- compatible: Must be ti,ti_fpdlink_dp_ser.
- reg: I2C address of the TI display serializer.
- ti_fpdlink_dp_ser-pwrdn: GPIO pin number of the PWRDN pin. This pin is used to power up the TI display serializer chip.
- timings-phandle: This property should be set as mode0 or mode1 to reflect raster or display timings used by the NVIDIA reference platforms.
- fpd-link-select: This property is an array of two unsigned 8-bit values that represent FPDlink port IDs. First field is for link A and the second is for link B. Value 0 indicates that the link is disabled and value 1 indicates that the link is enabled. At any given time, only one link is supported.
Optional properties:
- dprx-link-rate: Configures the DP link rate of the serializer chip.
  
  The default value is 0x1E (HBR3). The possible values are:
  - 0xA (HBR)
  - 0x14 (HBR2)
  - 0x1E (HBR3)
- dprx-lane-count: Configures the DP lane count of the serializer chip.
  
  The default value is 0x4. The possible values are:
  - 0x1
  - 0x2
  - 0x4

To enable to TI Maxim DP Serializer driver configuration on NVIDIA Reference Platform p3710, the bind partition command should be executed as follows:

bind_partitions -b p3710-12-a01 linux DISP_SER_MODULE=TI983