NvSIPLPipelineMgr.hpp

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/*
 * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */
 
#ifndef NVSIPLPIPELINEMGR_HPP
#define NVSIPLPIPELINEMGR_HPP
 
#include "NvSIPLCommon.hpp"
#include "NvSIPLClient.hpp"
#include "NvSIPLPlatformCfg.hpp"
#include "NvSIPLInterrupts.hpp"
 
#include <cstdint>
#include <vector>
 
namespace nvsipl
{
class NvSIPLPipelineNotifier
{
    static constexpr uint32_t MAX_DEVICE_GPIOS {8U};
 
public:
    enum NotificationType
    {
        NOTIF_INFO_ICP_PROCESSING_DONE = 0,
 
        NOTIF_INFO_ISP_PROCESSING_DONE = 1,
 
        NOTIF_INFO_ACP_PROCESSING_DONE = 2,
 
        NOTIF_INFO_CDI_PROCESSING_DONE = 3,
 
        NOTIF_INFO_ICP_AUTH_SUCCESS = 4,
 
        NOTIF_WARN_ICP_FRAME_DROP = 100,
 
        NOTIF_WARN_ICP_FRAME_DISCONTINUITY = 101,
 
        NOTIF_WARN_ICP_CAPTURE_TIMEOUT = 102,
 
        NOTIF_ERROR_ICP_BAD_INPUT_STREAM = 200,
 
        NOTIF_ERROR_ICP_CAPTURE_FAILURE = 201,
 
        NOTIF_ERROR_ICP_EMB_DATA_PARSE_FAILURE = 202,
 
        NOTIF_ERROR_ISP_PROCESSING_FAILURE = 203,
 
        NOTIF_ERROR_ACP_PROCESSING_FAILURE = 204,
 
        NOTIF_ERROR_CDI_SET_SENSOR_CTRL_FAILURE = 205,
 
        NOTIF_ERROR_DESERIALIZER_FAILURE = 207,
 
        NOTIF_ERROR_SERIALIZER_FAILURE = 208,
 
        NOTIF_ERROR_SENSOR_FAILURE = 209,
 
        NOTIF_ERROR_ISP_PROCESSING_FAILURE_RECOVERABLE = 210,
 
        NOTIF_ERROR_ICP_AUTH_FAILURE = 211,
 
        NOTIF_ERROR_INTERNAL_FAILURE = 300,
    };
 
    struct NotificationData
    {
        NotificationType eNotifType;
        uint32_t uIndex;
        uint8_t uLinkMask;
        uint64_t frameSeqNumber;
        uint64_t frameCaptureTSC;
        uint64_t frameCaptureStartTSC;
        InterruptCode intrCode;
        uint64_t intrData;
        uint32_t gpioIdxs[MAX_DEVICE_GPIOS];
        uint32_t numGpioIdxs;
    };
 
    virtual ~NvSIPLPipelineNotifier(void) = default;
};
 
class NvSIPLImageGroupWriter
{
public:
    struct RawBuffer
    {
        NvSciBufObj image;
        uint32_t uIndex;
        bool discontinuity;
        bool dropBuffer;
        uint64_t frameCaptureTSC;
        uint64_t frameCaptureStartTSC;
    };
 
    virtual SIPLStatus FillRawBuffer(RawBuffer &oRawBuffer) = 0;
 
    virtual ~NvSIPLImageGroupWriter(void) = default;
};
 
struct NvSIPLPipelineConfiguration
{
    bool captureOutputRequested {false};
 
    bool isp0OutputRequested {false};
 
    bool isp1OutputRequested {false};
 
    bool isp2OutputRequested {false};
 
    NvSIPLDownscaleCropCfg downscaleCropCfg {};
 
    NvSIPLIspStatsOverrideSetting statsOverrideSettings {};
 
    NvSIPLImageGroupWriter* imageGroupWriter {nullptr};
 
    bool disableSubframe {false};
};
 
class INvSIPLFrameCompletionQueue
{
public:
 
    virtual SIPLStatus Get(INvSIPLClient::INvSIPLBuffer*& item,
                           size_t const timeoutUsec) = 0;
 
    virtual size_t GetCount() const = 0;
 
protected:
 
    INvSIPLFrameCompletionQueue() = default;
    virtual ~INvSIPLFrameCompletionQueue() = default;
 
private:
 
    INvSIPLFrameCompletionQueue(INvSIPLFrameCompletionQueue const& other) = delete;
    INvSIPLFrameCompletionQueue& operator=(INvSIPLFrameCompletionQueue const& rhs) = delete;
};
 
class INvSIPLNotificationQueue
{
public:
 
    virtual SIPLStatus Get(NvSIPLPipelineNotifier::NotificationData& item,
                           size_t const timeoutUsec) = 0;
 
    virtual size_t GetCount() const = 0;
 
protected:
 
    INvSIPLNotificationQueue() = default;
    virtual ~INvSIPLNotificationQueue() = default;
 
private:
 
    INvSIPLNotificationQueue(INvSIPLNotificationQueue const& other) = delete;
    INvSIPLNotificationQueue& operator=(INvSIPLNotificationQueue const& rhs) = delete;
};
 
struct NvSIPLPipelineQueues
{
    INvSIPLFrameCompletionQueue* captureCompletionQueue {nullptr};
 
    INvSIPLFrameCompletionQueue* isp0CompletionQueue {nullptr};
 
    INvSIPLFrameCompletionQueue* isp1CompletionQueue {nullptr};
 
    INvSIPLFrameCompletionQueue* isp2CompletionQueue {nullptr};
 
    INvSIPLNotificationQueue* notificationQueue {nullptr};
};
 
struct NvSIPLDeviceBlockQueues
{
    INvSIPLNotificationQueue* notificationQueue[MAX_DEVICEBLOCKS_PER_PLATFORM];
};
 
}  // namespace nvsipl
 
 
#endif // NVSIPLPIPELINEMGR_HPP