NvSIPLISPStructs.hpp

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/*
 * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */
 
#ifndef NVSIPLISPSTRUCTS_HPP
#define NVSIPLISPSTRUCTS_HPP
 
#include "NvSiplControlAutoDef.hpp"
 
namespace nvsipl
{
constexpr uint32_t NUM_GTM_SPLINE_POINTS = 18U;
 
struct NvSiplISPGlobalToneMapInfo
{
    bool enable;
    NvSiplISPSplineControlPoint gtmSplineControlPoint[NUM_GTM_SPLINE_POINTS];
};
 
struct NvSiplControlInfo
{
    bool valid;
    float_t alpha;
    bool isLuminanceCalibrated;
    double_t luminanceCalibrationFactor;
    SiplControlAutoAwbGain wbGainTotal;
    float_t cct;
    float_t brightnessKey;
    float_t rawImageMidTone;
    NvSiplISPGlobalToneMapInfo gtmSplineInfo;
};
 
struct NvSIPLDownscaleCropCfg
{
    bool ispInputCropEnable {false};
    NvSiplRect ispInputCrop {};
 
    bool isp0OutputCropEnable {false};
    NvSiplRect isp0OutputCrop {};
 
    bool isp1OutputCropEnable {false};
    NvSiplRect isp1OutputCrop {};
 
    bool isp2OutputCropEnable {false};
    NvSiplRect isp2OutputCrop {};
 
    bool isp0DownscaleEnable {false};
    uint32_t isp0DownscaleWidth {0U};
    uint32_t isp0DownscaleHeight {0U};
 
    bool isp1DownscaleEnable {false};
    uint32_t isp1DownscaleWidth {0U};
    uint32_t isp1DownscaleHeight {0U};
 
    bool isp2DownscaleEnable {false};
    uint32_t isp2DownscaleWidth {0U};
    uint32_t isp2DownscaleHeight {0U};
 
};
 
} // namespace nvsipl
 
#endif // NVSIPLISPSTRUCTS_HPP