Bandwidth Computation

In general, camera data bandwidth is limited by the ISP, followed by VI and NVCSI. Furthermore, VI (through NVCSI) and ISP support 16 capture and processing input channels respectively.

NVCSI

NVCSI bandwidth is dependent on the Phy mode of the input stream, the number of lanes and trios, and the pixel data type. Higher bandwidth than the peak guidance published in the following table is achievable with shorter data types (such as RAW6/7).

Table: NVCSI maximum peak bandwidth


MIPI CSI-2 Phy mode		Clock frequency [MHz] (TEGRA234_CLK_NVCSI)
MIPI CSI-2 Phy mode		642.9
D-Phy	Per Lane [Gb/s]	2.5
D-Phy	Total [Gb/s]	40
C-Phy	Per Trio? [Gsym/s]	4.5
C-Phy	Total [Gb/s]	164.6

? C-PHY encodes bits in symbols at a 16:7 ratio (≈2.286 b/sym), and shifts in 16 BPC.

VI

NVCSI streams can map to two VI instances via the Device Tree. NVCSI pixel streams are synchronized to the VI clock domain (TEGRA234_CLK_VI), whose bandwidth scales approximately linearly with frequency.

Each VI instance accepts data from NVCSI streams at a rate of one packet per cycle, which yields a rate of 4 or 8 (≤ 16 BPP) pixels per clock depending on the pixel width (data type).

ISP

The ISP archives a maximum target throughput of two pixels per clock (TEGRA234_CLK_ISP). This may be limited by scheduling, memory latency, and tiling overhead.

A recommendation is to account for an additional 15% overhead for scheduling, memory and tiling latencies, and ISP PFSD (Permanent Fault Software Detection), which is enabled by default and always on.

Sample Calculations

This section calculates minimum required clocks for the use case, which must be satisfied by the power profile for all three camera engines: NVCSI, VI, and ISP.

Eight camera modules (4×IMX728@30 fps, 4×IMX623@30 fps, C-Phy, RAW12)

Total MP = 4*8.3 MP (IMX728) + 4*3.0 (IMX623) = 44.8 MP
Total BW: 44.8 MP * 12 BPP * 30 FPS = 16.128 Gb/s

== Minimum clocks configuration ==

NVCSI:
* Total BW < 164.6 Gb/s (in 4x C-Phy mode)
* Restrictions:
    (i) TEGRA234_CLK_NVCSI is fixed (642.9 MHz) for all available Power Profiles 
=> TEGRA234_CLK_NVCSI: 642.9 MHz

VI:
* Performance: 8 PPC (since 12 BPP ≤ 16 BPP)
* Required: 44.8 MP * 30 FPS / 8 PPC = 168 MHz
* Restrictions:
    (i) TEGRA234_CLK_VI ≥ TEGRA234_CLK_NVCSI (642.9 MHz)
=> TEGRA234_CLK_VI: 642.9 MHz

ISP:
* Performance: 2 PPC
* Required 44.8 MP * 30 FPS / 2 PPC = 672 MHz
* Additional: +15% for Tiling+ISP PFSD overhead
=> TEGRA234_CLK_ISP: 772.8 MHz