Camera Bandwidth Computation

The camera hardware pipeline on the Tegra SoC consists of three stages:

1. NVCSI - MIPI CSI-2 D/C-Phy receiver, deserializers or sensors (directly) interface here.
2. VI - CSI packet depacker/frame reassembly. Two instances, VI0 and VI1 are available for load balancing and redundancy.
3. ISP - Image Signal Processor.

NVCSI and VI are mandatory stages to receive external raw capture data, and frames are written into buffers in shared memory provided by the client.

These buffers are configured to be ingressed incrementally or all at once by the ISP before being output to another set of buffers in shared memory. Depending on the use case, the ISP stage may be selectively bypassed for individual channels.